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128 - position i 2 c- compatible digital resistor data sheet ad5246 re v. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p .o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2003 C 20 12 analog devices, inc. all rights reserved. features 128- position end - to - end resistance 5 k?, 10 k?, 50 k?, 100 k? ultracompact sc70 - 6 (2 mm 2.1 mm) package i 2 c? compatible interface full read/write of wiper register power - on preset to midscale single supply 2.7 v to 5.5 v rheostat mode temperatur e coefficient : 45 ppm/c low power, i dd = 0.9 a at 3.3 v typical wide operating temperature C 40c to +125c applications mechanical potentiometer replacement in new designs transducer adjustment of pressure, temperature, position, chemical, and optical s ensors rf amplifier biasing automotive electronics adjustment gain control and offset adjustment general overview the ad5246 provides a compact 2 mm 2.1 mm packaged solution for 128 - position adjustment applications. this device performs the same electro nic adjustment function as a variable resistor. available in four different end - to - end resistance values (5 k?, 10 k?, 50 k?, 100 k?), these low temperature coefficient devices are ideal for high accuracy and stability variable resistance adjustments. the wiper settings are controllable through the i 2 c compatible digital interface, which can also be used to read back the present wiper register control word. the resistance between the wiper and either end point of the fixed resistor varies linearly with resp ect to the digital code transferred into the rdac 1 latch. operating from a 2.7 v to 5.5 v power supply and consuming 0.9 a (3.3 v) allows for usage in portable battery - operated applications. 1 the terms digital potentiometer, vr, and rdac are used interch angeably in this document. functional block diagram i 2 c inter f ace wiper register sda scl gnd v dd a w b 03875-001 figure 1.
ad5246 data sheet rev. c | page 2 of 16 table of contents specifications ..................................................................................... 3 el ectrical characteristics 5 k? version .................................. 3 electrical characteristics 10 k?, 50 k?, 100 k? versions .. 4 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 6 esd caution ............................................................................ 6 pin configuration and funct ion descriptions ............................. 7 typical performance characteristics ............................................. 8 test circuits ..................................................................................... 11 i 2 c interface ..................................................................................... 12 operation ......................................................................................... 13 programming the variable resistor ......................................... 13 i 2 c compatible 2 - wire serial bus ........................................... 13 level shifting for bidirectional interface ................................ 14 esd protection ........................................................................... 14 terminal voltage operating range ......................................... 14 maximum operating current .................................................. 14 power - up seque nce ................................................................... 14 layout and power supply bypassing ....................................... 15 constant bias to retain resistance setting ............................. 15 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 5/12 rev. b to rev. c changes to features and general description sections .............. 1 changes to i dd parameters, table 1 ................................................ 3 changes to i dd parameters, table 2 ................................................ 4 changes to figure 10 ........................................................................ 9 rem oved evaluation board section ............................................. 15 changes to ordering guide .......................................................... 16 8 /0 9 rev. a to rev. b changes to power supply sensitivity parameter .......................... 3 updated outline dimen sions ........................................................ 16 changes to ordering guide ........................................................... 16 7 /05 rev. 0 to rev. a changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 4 changes to absolute maximum ratings ....................................... 6 moved pin configuration and function descriptions ................ 7 deleted table 7 ................................................................................ 12 changes to operation section ....................................................... 13 delet ed figur e 31 ............................................................................. 1 4 changes to f igure 30 and figure 32 ............................................. 14 9/03 revision 0: initial version
data sheet ad5246 rev. c | page 3 of 16 specifications electrical character istics 5 k ? version v dd = 5 v 10% or 3 v 10%; v a = +v dd ; C 40c < t a < +125c, unless otherwise noted. table 1 . parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nonlinearity 2 r -dn l r wb C 1.5 0.1 +1.5 lsb resistor integral nonlinearity 2 r - inl r wb C 4 0.75 +4 lsb nominal resistor tolerance 3 ?r ab t a = 25c C 30 +30 % resistance temperature coefficient ( ?r ab / r ab )/ ?t wiper = n o c onnect 45 ppm/c r w b r wb code = 0x00, v dd = 5 v 75 150 ? code = 0x00, v dd = 2.7 v 150 400 ? resistor terminals voltage range 4 v b, w gnd v dd v capacitance 5 b c b f = 1 mhz, measured to gnd, c ode = 0x40 45 pf capacitance 5 w c w f = 1 mhz, measured to gnd, c ode = 0x40 60 pf common - mode leakage i cm 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 5 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply current i dd v dd = 5.5 v; v ih = v dd or v il = gnd 3 7 a v dd = 5 v; v ih = v dd or v il = gnd 2.5 5.2 a v dd = 3 .3 v; v ih = v dd or v il = gnd 0.9 2 a power dissipation 6 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 40 w power supply sensitivity pssr v dd = +5 v 10%, c ode = m idscale 0.01 0.02 5 %/% dynamic characteristics 5 , 7 bandwidth C 3 db bw_5k r ab = 5 k ?, c ode = 0x40 1.2 mhz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.05 % v w settling time t s v a = 5 v, 1 lsb error b and 1 s resistor noise voltage density e n_wb r wb = 2.5 k?, r s = 0 ? 6 nv/hz 1 typical specifications represent average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error r - inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r - dnl measures the relative step change from ideal between successive tap posit ions. parts are guaranteed monotonic. 3 code = 0x7f. 4 resistor terminal a and resistor terminal w have no limitations on polarity with respect to each other. 5 guaranteed by design; not subject to production test. 6 p diss is calculated from (i dd v dd ). c mos logic level inputs result in minimum power dissipation. 7 v dd = 5 v.
ad5246 data sheet rev. c | page 4 of 16 electrical charact eristics 10 k ?, 50 k ?, 100 k ? versions v dd = 5 v 10% or 3 v 10%; v a = v dd ; C 40c < t a < +125c, unless otherwise noted. table 2 . parameter symbol conditions min typ 1 max unit dc characteristics, rheostat mode resistor di fferential nonlinearity 2 r - dnl r wb , v a = n o c onnect C 1 0.1 +1 lsb resistor integral nonlinearity 2 r - inl r wb , v a = n o c onnect C 2 0.25 +2 lsb nominal resistor tolerance 3 ?r ab t a = 25c C 20 +20 % resistance temperature c oefficient (?r ab /r ab )/?t wiper = no c onnect 45 ppm/c r wb r wb code=0x00, v dd = 5 v 75 150 ? code=0x00, v dd = 2.7 v 150 400 ? resistor terminals voltage range 4 v b, w gnd v dd v capacitance 5 b c b f = 1 mhz, m easured to gnd, c ode = 0x40 45 pf capacitance 5 w c w f = 1 mhz, measured to gnd, c ode = 0x40 60 pf common - mode leakage i cm 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 5 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply cu rrent i dd v dd = 5.5 v; v ih = v dd or v il = gnd 3 7 a v dd = 5 v; v ih = v dd or v il = gnd 2.5 5.2 a v dd = 3 .3 v; v ih = v dd or v il = gnd 0.9 2 a power dissipation 6 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 40 w power supply sensitivity pssr v dd = +5 v 10%, code = m idscale 0.01 0.02 %/% dynamic characteristics 5 , 7 bandwidth C 3 db bw r ab = 10 k?/50 k?/100 k?, c ode = 0x40 600/100/40 khz total harmonic distortion thd w v a = 1 v rms, f = 1 khz, r ab = 10 k? 0.05 % v w settling time (10 k?/50 k?/100 k?) t s v a = 5 v 1 lsb e rror b and 2 s resistor noise voltage density e n_wb r wb = 5 k?, r s = 0 9 nv/hz 1 typical specifications represent average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error r - inl is the deviation from an ideal value measured between the maxim um resistance and the minimum resistance wiper positions. r - dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 code = 0x7f. 4 resistor terminal a and resistor terminal w have no limitations on polarity with respect to each other. 5 guaranteed by design; not subject to production test. 6 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 7 all dynamic characteristics use v dd = 5 v.
data sheet ad5246 rev. c | page 5 of 16 timing characteristi cs v dd = 5 v 10% or 3 v 10%; v a = v dd ; C 40c < t a < +125c, unless otherwise noted. table 3 . parameter symbol conditions min typ 1 max unit i 2 c interface timing characteristics 2 , 3 , 4 scl clock frequency f scl 400 khz t buf bus free time b etween stop and start t 1 1.3 s t hd;sta hold time (repeated start) t 2 after this period, the first clock pulse is generate d 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 50 s t su;sta setup time for repeated start condition t 5 0.6 s t hd;dat data hold time t 6 0.9 s t su;dat data setup time t 7 100 ns t f fall time of both sda and scl signals t 8 300 ns t r rise time of both sd a and scl signals t 9 300 ns t su;sto setup time for stop condition t 10 0.6 s 1 typical spec ifications represent average readings at 25c and v dd = 5 v. 2 guaranteed by design; not subject to production test. 3 see timing diagrams ( figure 26, figure 27, and figure 28 ) for locations of measured values. 4 specifications apply to all parts.
ad5246 data sheet rev. c | page 6 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter value v dd to gnd C0.3 v to +7 v v a , v w to gnd v dd terminal current, aCb, aCw, bCw pulsed 1 20 ma continuous 5 ma digital inputs and output voltage to gnd 0 v to v dd + 0.3 v operating temperature range C40c to +125c maximum junction temperature (t jmax ) 150c storage temperature C65c to +150c lead temperature (soldering, 10 sec) 300c thermal resistance 2 ja : sc70-6 340c/w 1 maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissip ation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 package power dissipation = (t jmax ? t a )/ ja. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensiti ve device. electrostatic charges as hi gh as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
data sheet ad5246 rev. c | page 7 of 16 pin configuration an d function descripti ons v dd 1 gnd 2 scl 3 b 6 w 5 sda 4 ad5246 top view (not to scale) 03875-018 figure 2 . pin configuration table 5 . pin function descriptions pin o. mneonic description 1 v dd positive power supply. 2 gnd digital ground. 3 scl serial clock input. positive edge triggered. 4 sda serial data input/output. 5 w w terminal. 6 b b terminal.
ad5246 data sheet rev. c | page 8 of 16 typical performance characteristics code (decimal) rheostat mode inl (lsb) 0 ?1.0 0 0.2 1.0 16 32 48 64 80 96 112 128 ?0.8 ?0.6 ?0.4 ?0.2 0.4 0.6 0.8 v dd = 2.7v v dd = 5.5v t a = 25 c r ab = 10k ? rheostat mode inl (lsb) 03875-020 figure 3. r - inl vs. code vs. supply voltages code (decimal) rheostat mode dnl (lsb) 0 ?0.5 ?0.4 ?0.3 ?0.2 16 32 48 64 80 96 112 128 ?0.1 0 0.1 0.2 0.3 0.4 0.5 v dd = 2.7v v dd = 5.5v t a = 25 c r ab = 10k ? 03875-021 figure 4. r - dnl vs. code vs. supply voltages code (decimal) rheostat mode inl (lsb) 0 ?1.0 ?0.8 ?0.6 ?0.4 16 32 48 ?0.2 0 0.2 0.4 0.6 0.8 1.0 64 80 96 112 128 t a = ?40 c t a = +25 c t a = +85 c t a = +125 c t a = ?40 c t a = +85 c t a = +25 c t a = +125 c 03875-022 figure 5. r - inl vs. code vs. temperature code (decimal) rheostat mode dnl (lsb) 0 ?0.5 ?0.4 ?0.3 ?0.2 16 32 48 ?0.1 0 0.1 0.2 0.3 0.4 0.5 64 80 96 112 128 t a = ?40 c, +25 c, +85 c, +125 c ?40 c +25 c +85 c +125 c v dd = 2.7v r ab = 10k ? 03875-023 figure 6. r - dnl vs. code vs. temperature temperature ( c ) rheostat mode inl (lsb) ?40 ?3.0 ?0.5 0 ?25 ?10 5 20 35 50 65 80 ?2.5 ?2.0 ?1.5 ?1.0 fse, full-scale error (lsb) 95 110 125 v dd = 5.5v, v a = 5.5v v dd = 2.7v, v a = 2.7v 03875-024 figure 7 . full - scale error vs. temperature temperature ( c ) zse, zero-scale error (lsb) ?40 0 0.25 0.50 0.75 ?25 ?10 5 1.00 1.25 1.50 20 35 50 65 80 95 110 125 v dd = 5.5v, v a = 5.5v v dd = 2.7v, v a = 2.7v 03875-025 figure 8 . zero - scale error vs. temperature
data sheet ad5246 rev. c | page 9 of 16 temperature ( c ) i dd, supply current (a) ?40 0.01 0.1 1 10 ?25 ?10 100 5 20 35 50 65 80 95 110 125 v dd = 5.5v v dd = 2.7v digital inputs = 0v code = 0x40 03875-026 figure 9 . supply current vs. temperature 0 10 20 30 40 50 60 70 80 90 100 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121 rthesos ta t mode tempco (ppm/c) code (decimal) 5v 2.7v i wb = 200 a r ab = 10k 03875-027 figure 10 . rheostat mode tempco ? r wb / ?t vs. code gain (db) 10k ? 6 ?12 ?18 ?24 ?30 ?36 0 ?42 ?54 100k 1m 10m ?60 0x40 1k ?48 0x20 0x10 0x08 0x04 0x02 0x01 frequency (hz) 03875-028 figure 11 . gain vs. frequency vs. code, r ab = 5 k ? 10k ?6 ?12 ?18 ?24 ?30 ?36 0 ?42 ?54 100k 1m 10m ?60 0x40 1k ?48 0x20 0x10 0x08 0x04 0x02 0x01 gain (db) frequency (hz) 03875-029 figure 12 . gain vs. frequency vs. code, r ab = 10 k ? 10k ?6 ?12 ?18 ?24 ?30 ?36 0 ?42 ?54 100k 1m 10m ?60 0x40 1k ?48 0x20 0x10 0x08 0x04 0x02 0x01 gain (db) frequency (hz) 03875-030 figure 13 . gain vs. frequency vs. code, r ab = 50 k ? 10k ?6 ?12 ?18 ?24 ?30 ?36 0 ?42 ?54 100k 1m 10m ?60 0x40 1k ?48 0x20 0x10 0x08 0x04 0x02 0x01 gain (db) frequency (hz) 03875-031 figure 14 . gain vs. frequency vs. code, r ab = 100 k ?
ad5246 data sheet rev. c | page 10 of 16 10k ?6 ?12 ?18 ?24 ?30 ?36 0 ?42 ?54 100k 1m 10m ?60 5k? 1k ?48 50k? 10k? 100k ? gain (db) frequency (hz) 03875-032 figure 15 . C 3 db bandwidth @ code = 0x80 i dd (a) frequency (hz) 1k 0.25 0.20 0.15 0.30 0.10 0.05 10k 100k 1m 0 c t a = 25c a - v dd = 5.5v code = 0x55 b - v dd = 5.5v code = 0x7f c - v dd = 2.7v code = 0x55 d - v dd = 2.7v code = 0x7f d b a 03875-033 figure 16 . i dd vs. frequency v bias (v) 360 300 240 180 r wb (?) 120 60 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 t a = 25c r ab = 50k? code = 0x00 v dd = 2.7v v dd = 5.5v 03875-008 figure 17 . r wb vs. v bias vs. v dd v dd = 5.5v v b = 0v v w clk t a = 25c r ab = 10k? f clk = 100khz 5v 0v 03875-006 1s/div figure 18 . digital feedthrough v dd = 5.5v v b = 0v code 0x40 to 0x3f t a = 25c r ab = 10k? v w 200ns/div 03875-007 figure 19 . m idscale glitch, code 0x40 to 0x3f v dd = 5.5v v b = 0v code 00 h to 7f h v w t a = 25c r ab = 10k? i w = 50a 40s/div 1 03875-005 figure 20 . large signal settling time
data sheet ad5246 rev. c | page 11 of 16 test circuits figure 21 to figure 25 define the test conditions used in the product specificati on tables. i w v ms w b dut 03875-004 figure 21 . test circuit for resistor position nonlinearity error (rheostat operation; r - inl, r - dnl) ?v ms % dd % pss (% / %) = v + = v dd 10% psrr (db) = 20 log dut ms dd ( ) v dd v ms w b v + ?v ?v ?v 03875-009 figure 22 . test circuit for power supply sensitivity (pss, pssr) w 10k? 10k? 2.5v b +15v ?15v v out op27 dut v in 03875-010 figure 23 . test circuit for gain vs. frequency 03875-040 w b v dd to gnd dut i sw code = 0x00 r sw = 0.1v i sw 0.1v figure 24 . test circuit for incremental on resistance w b no connect i cm v cm dut 03875-012 figure 25 . test circuit for common - mode leakage current
ad5246 data sheet rev. c | page 12 of 16 i 2 c inte rface table 6 . write mode s 0 1 0 1 1 1 0 w a x d6 d5 d4 d3 d2 d1 d0 a p slave address byte data byte table 7 . read mode s 0 1 0 1 1 1 0 r a 0 d6 d5 d4 d3 d2 d1 d0 a p slave address byte data byte s = start condition. p = stop condition. a = acknowledge. x = dont care. w = write. r = read. d6, d5, d4, d3, d2, d1, d0 = data bits. t 1 t 3 t 4 t 2 t 7 t 8 t 9 p s p s t 10 t 5 t 9 t 8 scl sda t 2 t 6 03875-019 figure 26 . i 2 c interface, detailed timing diagram scl frame 1 frame 2 start by master ack by ad5246 slave address byte stop by master data byte sda 0 1 0 1 1 1 0 r/w x d6 d4 d3 d2 d1 d0 1 1 9 ack by ad5246 1 9 d5 03875-014 figure 27 . writing to the rdac register no ack by master scl sda 0 1 0 1 1 1 0 r/w 0 d6 d5 d4 d3 d2 d1 d0 1 9 1 9 frame 1 frame 2 start by master ack by ad5246 slave address byte rdac register stop by master 03875-013 figure 28 . reading from the rdac register
data sheet ad5246 rev. c | page 13 of 16 operation the ad5246 is a 128 - position, digitally controlled variable resistor (vr) device. programming the vari ab le resistor rheostat operation the nominal resistance of the rdac between t erminal a and terminal b is available in 5 k?, 10 k?, 50 k?, and 100 k?. the final two or three digits of the part number determine t he nominal resistance value, that is , 10 k? = 10, 50 k? = 50. the nominal resistance (r ab ) of the vr has 128 contact points accessed by the wipe r termina l . the 7 - bit data in the rdac latch is decoded to select one of the 128 possible settings. the general equation determining the digitally programmed output resistance between w and b is w ab wb r r d d r + = 2 128 ) ( (1) where: d is the decimal equiva lent of the binary code lo aded in the 7 - bit rdac register. r ab is the end - to - end resistance. r w is the wiper resistance contributed by the on resistance of each internal switch. bx wx ax d6 d4 d5 d2 d3 d1 d0 rdac latc and decoder r s r s r s 03875-015 figure 29 . ad5246 equivalent rdac circuit note t hat in the zero - scale condition, there is a relatively small finite wiper resistance . care should be taken to limit the current flow between w and b in this state to a maximum pulse current of no more than 20 ma. otherwise, degradation or possible destruct ion of the internal switch contact can occur. typical device - to - device matching is process lot dependent and may vary by up to 30%. since the resistance element is proc - essed in thin - film technology, the temperature coefficient of r ab is only 45 ppm/c. i 2 c compatible 2 - wire serial bus the first byte of the ad5246 is a slave address byte (see table 6 and table 7 ). it has a 7 - bit slave address and a n r/ w bit. the seven msbs of the slave address are 0101110 followed by 0 for a write command or 1 to place the device in read mode. the 2 - wire i 2 c serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when a high - to - low transit ion on the sda line occurs while scl is high (see figure 27 ). the following byte is the slave address byte, which consists of the 7 - bit slave address followed by an r/ w bit (this bit determines whether data will be read from or written to the slave device). the slave whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bu s remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is high, the master read s from the slave device. conversely , if the r/ w bit is low, the master writ e s to the slave device. 2. in write mode, after acknowledgement of the slave address byte, the next byte is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transiti ons on the sda line must occur during the low period of scl and remain stable during the high period of scl (see table 6 ). 3. in read mode, after acknowledgment of the slave address byte, data is received over the serial bus in seque nces of nine clock pulses (a slight difference from the write mode where eight data bits are followed by an acknowledge bit). similarly, the transitions on the sda line must occur during the low period of scl and remain stable during the high period of sc l (see figure 28). 4. when all data bits have been read or written, a stop condition is established by the master. a stop condition is defined as a low - to - high transition on the sda line while scl is high . in write mode, the master pull s the sda line high during the tenth clock pulse to establish a stop condition (see figure 27 ). in read mode, the mast er issue s a no acknowledg e for the ninth clock pulse (that is , the sda lin e remains high). the master then brings the sda line low before the tenth clock pulse, which goes high to establish a stop condition (see figure 28).
ad5246 data sheet rev. c | page 14 of 16 a repeated write function gives the user flexibility to update the rdac output a number of times after addressin g the part only once. for example, after the rdac has acknowledged its slave address in write mode, the rdac output update s on each succes - sive byte. if different instructions are needed, the write/read mode has to start again with a new slave address and data byte. similarly, a repeated read function of the rdac is also allowed. level shifting for b idirectional interfa ce while most legacy systems may be operated at one voltage, a new component may be optimized at another. when two systems operate the same signal at two different voltages, proper level shifting is needed. for instance, one can use a 1.8 v e 2 prom to interface with a 5 v digital potentiometer. a level shifting scheme is needed to enable a bidirectional communi - cation so that the setting of th e digital potentiometer can be stored to and retrieved from the e 2 prom. figure 30 shows one of the implementations. m1 and m2 can be any n channel signal fets, or if v dd falls below 2.5 v, m1 and m2 can be low threshold fets such as the fdv301n. e 2 prom ad5246 sda1 scl1 d g r p r p 1.8v 5v s m1 scl2 sda2 r p r p g s m2 v dd1 = 1.8v v dd2 = 5v d 03875-011 figure 30 . level shifting for operation at different potentials esd protection all digital inputs are protected with a series input resistor and parallel zener esd structures , as shown in figure 31. this applies to the digital input pins sda and scl. logic 340 ? gnd 03875-002 figure 31 . esd protection of digital pins terminal voltage ope rating range the ad5246 v dd and gnd power supply defines the boundary conditions for proper 3 - te rminal digital potentiometer operat ion. supply signals present on t erminal b and terminal w that exceed v dd or gnd are clamped by the internal forward biased diodes (see figure 32). b v dd w gnd 03875-016 figure 32 . maximum t erminal voltages set by v dd and gnd maximum o perating current at low code values, the user should be aware that due to low resistance values, the current through the rdac may exceed the 5 ma limit. in figure 33 , a 5 v supply is p laced on the wiper, and the current through t erminal w and terminal b is plotted with respect to code. a line is also drawn denoting the 5 ma current limit. note that at low code values (particularly for the 5 k and 10 k options), the current level increases significantly. care should be taken to limit the current flow between w and b in this state to a maximum continuous current of 5 ma and a maximum pulse current of no more than 20 ma. otherwise, degradation or possible destruction of the internal switch contacts can occur. code (decimal) iwb current (ma) 0 0.01 0.1 1 10 16 32 48 64 80 96 112 128 100 5ma current limit r ab = 5k? r ab = 10k? r ab = 100k? r ab = 50k? 03875-034 figure 33 . maximum operating current power - up sequence since the esd protection diodes limit the voltage compliance at terminal b and terminal w (see figure 32 ), it is important to power v dd /gnd before applying any voltage to terminal b and terminal w; otherwise, the diode is forward biased such that v dd is powered unintentionally and may affect the rest of the users circuit. the ide al power - up sequence is in the follow - ing order: gnd, v dd , digital inputs, and then v b /v w . the relative order of powering v b and v w and the digital inputs is not important, providing they are powered after v dd /gnd.
data sheet ad5246 rev. c | page 15 of 16 layout and power sup ply bypassing it is a good practice to use a compact, minimum lead - length layout design. the leads to the inputs should be as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is good practice to bypa ss the power supplies with quality capacitors for optimum stability. supply leads to the device should be bypassed with 0.01 f to 0.1 f disc or chip ceramic capacitors. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at t he supplies to minimize any transient disturbance and low frequency ripple (see figure 34 ). note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce. ad5246 v dd c1 c3 gnd 10f 0.1f + v dd 03875-017 figure 34 . power supply bypassing constant bias to r etain r esistance s etting for users who desire nonvolatility but cannot justify the addi - tional cost for the eemem, the ad5246 may be considered as a low cost alternative by maintaining a constant bias to retain the wiper setting. the ad5246 was designed specifically with low power in mind, which allows low power consumption eve n in battery - operated systems. the graph in figure 35 demonstrates the power consumptio n from a 3.4 v 450 ma / hr li - ion cell phone battery, which is connected to the ad5246. the measurement over time shows that the device draws approximately 1.3 a and consumes negligible power. over a course of 30 days, the battery was depleted by less than 2%, the majority of which is due to the intrinsic leakage current of the battery itself. days battery life depleted 0 90% 92% 94% 96% 5 10 15 98% 100% 102% 104% 106% 108% 110% 20 25 30 t a = 25 c 03875-035 figure 35 . battery operating life depletion this demonstrates that constantly biasing the pot is not an impractical approach. most port able devices do not require the removal of batteries for the purpose of charging. although the resistance setting of the ad5246 will be lost when the battery needs replacement, such event s occur rather infrequently, so that this inconvenience is justified by the lower cost and smaller size offered by the ad5246. if and when total power is lost, the user should be provided with a means to adjust the setting accordingly.
ad5246 data sheet rev. c | page 16 of 16 outline dimensions 1 . 3 0 b s c complian t to je dec standards mo-203-ab 1 . 0 0 0 . 9 0 0 . 7 0 0 . 4 6 0 . 3 6 0 . 2 6 2 . 2 0 2 . 0 0 1 . 8 0 2 . 4 0 2 . 1 0 1 . 8 0 1 . 3 5 1 . 2 5 1 . 1 5 072809 -a 0 . 1 0 m a x 1 . 1 0 0 . 8 0 0 . 4 0 0 . 1 0 0 . 2 2 0 . 0 8 3 1 2 4 6 5 0 . 6 5 b s c coplan arity 0.10 sea ting plane 0 . 3 0 0 . 1 5 figure 36 . 6 - lead thin shrink small out line transistor package [sc70] (ks - 6) dimensions shown in millimeters ordering guide model 1 , 2 r ab (k?) temperature range package description package option branding ad5246bksz5 - rl7 5 C 40c to +125c 6 - lead sc70 ks -6 d93 ad5246bksz10 -r2 10 C 40c to +125 c 6 - lead sc70 ks -6 d92 ad5246bksz10 - rl7 10 C 40c to +125c 6 - lead sc70 ks -6 d92 ad5246bksz50 - rl7 50 C 40c to +125c 6 - lead sc70 ks -6 d94 ad5246bksz100 -r2 100 C 40c to +125c 6 - lead sc70 ks -6 d9d ad5246bksz100 - rl7 100 C 40c to +125c 6 - lead sc70 ks -6 d 9d eval - ad5246dbz evaluation board 1 z = rohs compliant part. 2 the evaluation board is shipped with the 10 k ? r ab resistor option; however, the board is compatible with all available resistor value options. purchase of licensed i 2 c components of analog dev ices or one of its sublicensed associated companies conveys a license for the purchaser under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2003 C 20 12 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d 0387 5C0 C5 / 12 ( c )

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